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V DD Bypass Capacitor Guidelines
To enable this IC to turn a device on quickly, a local
high-frequency bypass capacitor, C BYP , with low ESR
and ESL should be connected between the VDD and
?
best results, make connections to all pins as short
and direct as possible.
The turn-on and turn-off current paths should be
minimized, as discussed above.
GND pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10μF to 47μF
commonly found on driver and controller bias circuits.
A typical criterion for choosing the value of C BYP is to
keep the ripple voltage on the V DD supply to ≤ 5%. This
is often achieved with a value ≥ 20 times the equivalent
load capacitance C EQV , defined as Q GATE /V DD . Ceramic
capacitors of 0.1μF to 1μF or larger are common
choices, as are dielectrics, such as X5R and X7R, with
stable temperature characteristics and high pulse
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure the part is operating within
acceptable temperature limits.
The total power dissipation in a gate driver is the sum of
two components, P GATE and P DYNAMIC :
current capability.
P TOTAL =P GATE + P DYNAMIC
(1)
If circuit noise affects normal operation, the value of
C BYP may be increased to 50-100 times the C EQV or C BYP
may be split into two capacitors. One should be a larger
value, based on equivalent load capacitance, and the
other a smaller value, such as 1-10nF, mounted closest
to the VDD and GND pins to carry the higher-frequency
components of the current pulses. The bypass capacitor
must provide the pulsed current from both of the driver
channels and, if the drivers are switching
simultaneously, the combined peak current sourced
from the C BYP can be twice as large as when a single
channel is switching.
Layout and Connection Guidelines
The FAN3278 gate driver incorporates fast-reacting
input circuits, short propagation delays, and powerful
output stages capable of delivering current peaks over
1.5A to facilitate fast voltage transition times. The
following layout and connection guidelines are strongly
recommended:
? Keep high-current output and power ground paths
separate from logic and enable input signals and
signal ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.
? Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that results
from driving a MOSFET with a specified gate-source
voltage, V GS , with gate charge, Q G , at switching
frequency, f SW , is determined by:
P GATE =Q G ? V GS ? f SW (2)
This needs to be calculated for each P-channel and N-
channel MOSFET where the Q G is likely to be different.
Dynamic Pre-drive / Shoot-through Current: Power loss
resulting from internal current consumption under
dynamic operating conditions, including pin pull-up /
pull-down resistors, can be obtained using the “I DD (No-
Load) vs. Frequency” graphs in Figure 9 to determine
the current I DYNAMIC drawn from V DD under actual
operating conditions.
P DYNAMIC =I DYNAMIC ? V DD (3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming ψ JB was determined for a similar thermal
design (heat sinking and air flow):
T J =P TOTAL ? ψ JB + T B (4)
?
reduces the series inductance to improve high-
speed switching, while minimizing the loop area
that can couple EMI to the driver inputs and
surrounding circuitry.
If the inputs to a channel are not externally
connected, the internal 100k Ω resistors indicated
on block diagrams command a low output on
channel A and a high output on channel B. In noisy
environments, it may be necessary to tie inputs of
an unused channel to VDD or GND using short
traces to prevent noise from causing spurious
output switching.
where:
T J =driver junction temperature
ψ JB =(psi) thermal characterization parameter relating
temperature rise to total power dissipation
T B =board temperature in location defined in
Note 1 under Thermal Resistance table.
As an example of a power dissipation calculation,
consider an application driving two MOSFETs (one P-
channel and one N-channel, both with a gate charge of
60nC each) with V GS =V DD =12V. At a switching
frequency of 200kHz, the total power dissipation is:
?
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output mis-
triggering. These effects can be obvious if the
P GATE =60nC ? 12V ? 200kHz ? 2=0.288W
P DYNAMIC =1.65mA ? 12V =0.020W
P TOTAL =0.308W
(5)
(6)
(7)
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
? 2010 Fairchild Semiconductor Corporation
FAN3278 ? Rev. 1.0.1
11
www.fairchildsemi.com
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